Model number: cmpslurry
In advanced semiconductor manufacturing, Chemical Mechanical Polishing (CMP) is a critical step for wafer planarization.
Scientia leverages high-quality CMP slurry products from leading supplier to provide a comprehensive portfolio covering oxide, tungsten, polysilicon and ceria-based slurries. These products help customers balance removal rate, selectivity and defect control across different process steps and achieve a stable, high-yield process window.
The portfolio is organized into four major series by material type, covering typical front-end applications such as ILD, STI, W plug, polysilicon gate and related structures:
Oxide Slurry
Tungsten Slurry
Polysilicon Slurry
Ceria Slurry
Precise control of solid content and dilution ratio
Using colloidal silica or ceria as the abrasive base, each formulation is designed with specific solid content and recommended dilution ratios. This enables operating conditions ranging from high removal rate to mild polishing, and allows flexible tuning according to process requirements.
Balanced planarization and defect performance
All slurry series are designed to deliver excellent planarization capability while maintaining low scratch and low defect levels, helping reduce downstream cleaning effort and rework cost.
Stable dispersion and storage performance
The slurries feature narrow particle size distribution and good suspension stability, minimizing sedimentation and large-particle agglomeration, and supporting long-term, continuous production.
Designed for oxide layer planarization, such as ILD and STI processes.
DI-3000
Colloidal silica-based
Medium-to-high solid content, balancing removal rate and surface quality
Suitable for production lines that require higher throughput
DI-3100
Colloidal silica-based, high solid content design
Provides faster removal rate and excellent planarization
Recommended as a main oxide CMP formulation
DI-9000
Colloidal silica-based with low solid content, recommended for 5–10× dilution
Suitable for final polish steps or processes that are highly sensitive to surface defects
Formulated for tungsten plug fill, W plug and related tungsten processes, with emphasis on removal rate and selectivity control.
TN-2000 / TN-2001
Fumed silica-based
Approx. 5% solid content, recommended for 2–4× dilution
Balances stable removal rate with cost-effectiveness
TN-1020 / TN-2020
Colloidal silica-based formulations
Designed for lower selectivity and excellent planarization
Suitable for processes requiring precise control of tungsten versus dielectric removal
TN-1030
Colloidal silica-based formulation
Provides higher selectivity while maintaining good planarization performance
Ideal for new node development and process evaluation
TB-1000
Post-CMP buff polishing slurry
Helps further reduce defects and surface roughness
Suitable as the final step in tungsten CMP
Used for planarization and pattern refinement of polysilicon gates, resistors and related structures.
PS-2003
Colloidal silica-based
Recommended for 10–20× dilution
Supports high-throughput volume production lines
PS-2008
Recommended dilution range of 4–10×
Suitable for polysilicon processes requiring a balance of removal rate and surface quality
PS-2100
Custom formulation developed for specific 12-inch fab process conditions
Can be further tuned for other lines or process steps as needed
PS-2102
Colloidal silica slurry dedicated for polysilicon
Designed to balance removal rate, uniformity and defect performance
PS-3000
Recommended for 10–20× dilution
Suitable as a standard slurry for high-productivity, multi-tool deployments
Mainly used for demanding oxide or specific dielectric CMP processes.
CE-3000
Ceria-based slurry, recommended at around 4× dilution
Offers excellent chemical activity and polishing selectivity
Suitable for planarization of critical dielectric or high-k layers
CE-5000
Provides a wide operation window with approx. 4–10× dilution
Flexible process tuning according to on-line conditions
Ideal for development phases involving new materials or new device structures
ILD / STI planarization in advanced logic processes
Tungsten plug, metal gate and contact-hole polishing
Polysilicon gate and resistive structure planarization
Precision planarization of special dielectrics and high-k layers
Other CMP processes requiring both high removal rate and low-defect performance